1. Technical Field
This disclosure relates to memory systems and more specifically to pipelined memory circuits.
2. Description of the Related Art
Most computer systems invariably use some form of random access memory (RAM). Often in volatile memory applications a memory device in the dynamic RAM (DRAM) family is used due to cost considerations. Like any memory, DRAM has an inherent amount of time that it takes for data to appear at the DRAM output after a read command has been received at the DRAM input. This is typically referred to as the read latency or the access time. To mitigate some of this read latency, one type of DRAM, known as synchronous DRAM, is implemented using a pipelined architecture in which read latency stretches over multiple cycles but new commands are issued every cycle. Using this technique, the effective data output bandwidth of the device may be increased, which corresponds to a reduced read cycle time. When a pipelined architecture is used, the phrase read cycle time is typically used to refer to the time or the period between successive read data output cycles.
Many conventional pipelined memory devices employ a number of sequential logic clocked storage devices such as latches, flip-flops, and the like in the read address path and the data output clock path. These sequential logic devices may be clocked by the system clock or some derivative thereof. Accordingly, for a given system clock frequency, the memory device will have a corresponding cycle time. However, as the system clock frequency varies, the memory cycle time will be vary. This differing read cycle time can be problematic when attempting to maintain relatively constant latency for various clock frequencies.